1. Field of the Invention
The present invention relates to an electrically erasable programmable non-volatile semiconductor memory device, for example, a NAND-type EEPROM.
2. Description of the Related Art
An electrically erasable programmable read-only memory (EEPROM) has been known in the art as one of semiconductor memories. For example, a NAND-type EEPROM including NAND cells has received attention because it can be highly integrated. Each NAND cell consists of a plurality of serially connected memory cells, each of which is the unit of one bit memory. The NAND-type is utilized in a memory card to store image data output from a digital still camera, for example.
The memory cell in the NAND-type EEPROM has an FET-MOS structure that includes a floating gate and a word line layered via insulators on a semiconductor substrate that provides a channel region. The NAND cell includes a plurality of memory cells serially connected in such a manner that they share a source/drain between neighbors. The source/drain corresponds to an impurity region that functions as at least one of a source and a drain.
An exemplary method of programming data in the NAND-type is described simply.
(1) “0” Program
While a channel region is kept at a voltage of 0V, a word line corresponding to a memory cell for “0” program is selected, and a voltage of 20V is applied to the word line. In addition, a voltage, for example, of 10V is applied to the word lines other than the selected word line. Because of a large potential difference between the selected word line and the channel region, electrons are injected through the tunnel current into the floating gate of the memory cell. As the result, the threshold of the memory cell turns to a positive state (“0” programmed state).
(2) “1” Program
After the channel region is set in a floating state at a certain voltage above 0V, a word line corresponding to a memory cell for “1” program is selected, and a voltage of 20V is applied to the word line likewise “0” program. In addition, a voltage, for example, of 10V is applied to the word lines other than the selected word line. As a result, the voltage on the channel region is boosted up, for example, to 8V through capacitive coupling with the selected word line. In this case, different from “0” program, because of a small potential difference between the selected word line and the channel region, few electrons are injected through the tunnel current into the floating gate of the memory cell for “1” program. Therefore, the threshold of the memory cell is retained in a negative state (“1” programmed state).
For “1” program, if the elevation of the voltage on the channel region is small, the tunnel current injects electrons into the floating gate, resulting in “0” program. In order to prevent such the failed program, in another exemplary programming method, a voltage of 0V is applied to two word lines both located adjacent to the word line for the memory cell for “1” program to increase the voltage elevation on the channel region.
The word lines are provided with respective transfer transistors. This transistor is employed to apply a voltage to the word line. According to the other exemplary programming method, the selected word line is set at 20V, the both adjacent word lines at 0V, and other word lines at 10V for programming. Therefore, transfer transistors may be required to supply 20V, 10V and 0V to the corresponding word lines.
A device isolation insulator for use in isolation between transfer transistors is required to have such a breakdown voltage that is determined based on the largest potential difference between adjacent transistors, specifically a potential difference when one of the adjacent transistors is set at 20V and the other at 0V. Therefore, compared to the exemplary programming method that does not utilize 0V, the device isolation insulator is required to have a higher breakdown voltage. This requirement increases the dimension of the device isolation insulator, and accordingly increases the area of a region to locate the transfer transistor (that is, an area of a row decoder). A technology has been known to devise arrangement of the transfer transistors to prevent such the problem (for example, Japanese Patent Application laid-Open No. 2002-141477, FIGS. 1 and 2).